Exclusive: Artificial Intelligence

Present situation and future trend of artificial intelligence chips

  • YIN Shouyi ,
  • GUO Heng ,
  • WEI Shaojun
  • Institute of Microelectronics, Tsinghua University, Beijing 100083, China

Received date: 2018-08-17

  Revised date: 2018-08-27

  Online published: 2018-09-18


The artificial intelligence chips (AI) chip is an important part of artificial intelligence technology. It is the hardware foundation of AI algorithm and the essential of the AI era. This paper analyzes the state of the art, characteristics, potential technical trends and marketing of AI chips, and forecasts the opportunities, challenges and future trends faced by AI chips.

Cite this article

YIN Shouyi , GUO Heng , WEI Shaojun . Present situation and future trend of artificial intelligence chips[J]. Science & Technology Review, 2018 , 36(17) : 45 -51 . DOI: 10.3981/j.issn.1000-7857.2018.17.006


[1] 人工智能产业发展研究课题组. 北京人工智能产业发展白皮书(2018年)[R/OL]. (2018-06-30)[2018-07-01]. http://jxw.beijing.gov.cn/docs/2018-07/20180704102639512942.pdf. Research Group on the Development of Artificial Intelligence Industry. Beijing artificial intelligence industry development white paper (2018)[R/OL]. (2018-06-30)[2018-07-01]. http://jxw.beijing.gov.cn/docs/2018-07/20180704102639512942.pdf.
[2] 朱晶. 对国内人工智能芯片产业格局的观察[EB/OL].[2018-03-05]. https://mp.weixin.qq.com/s/f_4NZB7XwoGlNtsJOT4HQQ?tdsourcetag=s_pctim_aiomsg. Zhu Jing. Observation on the structure of AI chip industry in China[EB/OL].[2018-03-05]. https://mp.weixin.qq.com/s/f_4NZB7XwoGlNtsJOT4HQQ?tdsourcetag=s_pctim_aiomsg.
[3] 中国电子技术标准化研究院. 人工智能标准化白皮书(2018版)[R/OL].[2018-03-31]. http://www.cesi.ac.cn/images/editor/20180124/20180124135528742.pdf. China Electronics Standardization Institute. Artificial intelligence standardization white paper (2018 Edition)[R/OL].[2018-03-31]. http://www.cesi.ac.cn/images/editor/20180124/2018012-4135528742.pdf.
[4] 吴军宁. AI芯片格局最全分析[EB/OL]. (2018-04-01)[2018-07-30]. http://www.sohu.com/a/226935100_132567. Wu Junning. The most complete analysis of AI chip pattern[EB/OL]. (2018-04-01)[2018-07-30]. http://www.sohu.com/a/2269-35100_132567.
[5] Mead C. Neuromorphic electronic systems[J]. Proceedings of the IEEE, 1990, 78(10):1629-1636.
[6] Silver D, Huang A, Maddison C J, et al. Mastering the game of Go with deep neural networks and tree search[J]. Nature, 2016, 529(7587):484-489.
[7] Gaster B, Howes L, Kaeli D R, et al. Heterogeneous computing with OpenCL:Revised OpenCL 1.2 edition[M]. San Francisco:Morgan Kaufmann Publishers Inc., 2012.
[8] 韩俊刚, 刘有耀, 张晓. 图形处理器的历史现状和发展趋势[J]. 西安邮电大学学报, 2011, 16(3):61-64. Han Jungang, Liu Youyao, Zhang Xiao. GPU:The past, present and future[J]. Journal of Xi'an University of Posts and Telecommunications, 2011, 16(3):61-64.
[9] Jeff Dorsch. 现场可编程门阵列FPGA芯片及其应用[J]. 集成电路应用, 2018(1):77-79. Jeff Dorsch. FPGAs for all seasons[J]. Applications of IC, 2018(1):77-79.
[10] Gschwind M, Hofstee H P, Flachs B, et al. Synergistic processing in cell's multicore architecture[J]. IEEE Micro, 2006, 26(2):10-24.
[11] De Dinechin B D, Ayrignac R, Beaucamps P E, et al. A clustered manycore processor architecture for embedded and accelerated applications[C]//High Performance Extreme Computing Conference. Piscataway NJ:IEEE, 2013, doi:10.1109/HPEC.2013.6670342.
[12] Sodani A. Knights landing (KNL):2nd Generation Intel® Xeon Phi processor[C]//2015 IEEE Hot Chips 27 Symposium (HCS). Piscataway NJ:IEEE, 2015, doi:10.1109/HOTCHIPS. 2015.7477467.
[13] Jouppi N P, Young C, Patil N, et al. In-datacenter performance analysis of a tensor processing unit[C]//2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA). Piscataway NJ:IEEE, 2017:1-12.
[14] 中国类脑强人工智能初创公司——西井科技实现全球首次"片上学习"[EB/OL].[2018-03-31]. http://www.sh.chinanews.com.cn/kjws/2016-09-17/11052.shtml. The westwell realize the first "on-chip learning" in the world[EB/OL].[2018-03-31]. http://www.sh.chinanews.com.cn/kjws/2016-09-17/11052.shtml.
[15] 魏少军. 从IA到AI,我们还要走多远[C]. 2018全球人工智能与机器人峰会, 深圳,2018-07-01. Wei Shaojun. How far do we need to go from IA to AI[C]. 2018 Global Artificial Intelligence and Robotics Summit, Shenzhen, July 1, 2018.
[16] Halfhill T R. XMOS重新定义晶圆-软件定义芯片挑战ASIC、ASSP以及FPGA[J]. 电子产品世界, 2007(10):80-84. Halfhill T R. XMOS redefines siliconsoftware-defined chips attack ASICs, ASSPs, FPGAs[J]. Electronic Engineering & Product World, 2007(10):80-84.
[17] Hartenstein R. A decade of reconfigurable computing:A visionary retrospective[C]//Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001. 2001:642-649.
[18] Yin S, Ouyang P, Tang S, et al. A high energy efficient reconfigurable hybrid neural network processor for deep learning applications[J]. IEEE Journal of Solid-State Circuits, 2018, 53(4):968-982.
[19] Yin S Y, Ouyang P, Tang S, et al. A high energy efficient reconfigurable hybrid neural network processor for deep learning applications[J]. IEEE Journal of Solid-State Circuits, 2018, 53(4):968-982.
[20] Yin S Y, Zheng S X, Song D D. A 141μW, 2.46 pJ/neuron binarized convolutional neural network based self-learning speech recognition processor in 28 nm CMOS[C]. 2018 Symposia on VLSI Technology and Circuits, Honolulu,June 18-22, 2018.
[21] Sun Y T. China wants to make the chips that will add AI to any gadget[EB/OL]. (2018-01-24)[2018-03-31]. https://www.technologyreview.com/s/609954/china-wants-to-make-the-chips-that-will-add-ai-to-any-gadget/.
[22] 中国电子学会. 新一代人工智能发展白皮书(2017年)[R/OL]. (2018-03-05)[2018-06-30]. http://www.199it.com/archives/694966.html. Chinese Society of Electronics. White paper on the development of the new generation of artificial intelligence (2017)[R/OL]. (2018-03-05)[2018-06-30]. http://www.199it.com/archives/694966.html.
[23] Barrus J. Cloud TPU machine learning accelerators now available in beta[EB/OL]. (2018-02-12)[2018-03-31]. https://chinagdg.org/2018/02/cloud-tpu-machine-learning-acceleratorsnow-available-in-beta/.
[24] Naveen R. Intel® NervanaTM neural network processors (NNP) redefine AI silicon[EB/OL]. (2017-10-17)[2018-03-31]. https://ai.intel.com/intel-nervana-neural-network-processorsnnp-redefine-ai-silicon/.
[25] Chua R. 2017 innovations in edge computing and MEC report[R]. Denver:SDxCentral, 2017.
[26] Liu S, Du Z, Tao J, et al. Cambricon:An instruction set architecture for neural networks[C]//International Symposium on Computer Architecture. Piscataway NJ:IEEE, 2016:393-405.
[27] 孙永杰.地平线:架构创新BPU算法+芯片+云一体化[J]. 通信世界, 2018(13):31. Sun Yongjie. Horizon Robotics:Architecture innovation BPU algorithm + chip + cloud integration[J]. Communications World, 2018(13):31.
[28] Han S, Mao H, Dally W J. Deep compression:Compressing deep neural networks with pruning, trained quantization and huffman coding[J]. Fiber, 2015, 56(4):3-7.
[29] 宋继强, 魏少军. AI芯片:从历史看未来[EB/OL]. (2018-07-20)[2018-07-31]. http://36kr.com/p/5144249.html. Song Jiqiang, Wei Shaojun. AI chip:Looking at the future from the perspective of history[EB/OL]. (2018-07-20)[2018-07-31]. http://36kr.com/p/5144249.html.
[30] Luker P A, Rothermel D. The philosophy of artificial intelligence[J]. ACM Sigcse Bulletin, 1990, 26(1):41-45.
[31] AI芯片终极难题被清华大学IC男神解决了[EB/OL]. (2018-02-12)[2018-03-31]. http://zhidx.com/p/109515.html. The ultimate problem of AI chip is solved[EB/OL]. (2018-02-12)[2018-03-31]. http://zhidx.com/p/109515.html.